1. Field of the Invention
This invention relates generally to programmable logic devices, and in particular to a system and method for time multiplexing the programmable interconnect of a field programmable gate array.
2. Description of the Related Art
Programmable logic devices such as field programmable gate arrays (“FPGAs”) are a well-known type of integrated circuit and are of wide applicability due to the flexibility provided by their reprogrammable nature. An FPGA typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other to provide logic functions desired by a user (a circuit designer). An FPGA typically includes a regular array of identical CLBs, wherein each CLB is individually programmed to perform any one of a number of different logic functions. These functions may include logic in lookup tables (LUTs) and storage in flip-flops or latches. The FPGA may also include tri-state buffers that users may use to share routing wires. The FPGA has a configurable routing structure called a programmable interconnect (hereinafter interconnect) for interconnecting the CLBs according to the desired user circuit design. The FPGA also includes a number of configuration memory cells which are operatively coupled to the CLBs to specify the function to be performed by each CLB, as well as to the interconnect to specify the coupling of the input and output lines of each CLB.
One approach available in the prior art to increase the functionality of logic circuits has been increasing the number of CLBs and interconnect structures in the FPGA. However, for any given semiconductor fabrication technology, there are limitations to the number of CLBs that can be fabricated on an integrated circuit chip of practical size. Thus, there continues to be a need to increase the number of logic gates or CLB densities for FPGAs.
Because the chip area of programmable logic devices is dominated by interconnect area, methods have been proposed for sharing this interconnect. In one approach, a user uses tri-state buffers or multiplexers to place different signals into a wire at different times. The user can build circuitry in the programmable logic to control the tri-state buffers or multiplexers, and to capture the desired signals at their destination. Unfortunately, this method requires a significant amount of programmable logic and interconnect resources which may be greater than the amount saved by sharing the interconnect.
Another approach to increase the functionality of logic circuits has been the reconfiguration of the FPGA. Unfortunately, this reconfiguration requires the time consuming step of reloading a configuration bit stream for each reconfiguration. Moreover, reconfiguration of an FPGA generally requires suspending the implementation of the logic functions, saving the current state of the logic functions in a memory device external to the FPGA, reloading the entire array of memory configurations cells, and inputting the states of the logic functions, which have been saved off chip along with any other needed inputs. Each of these steps requires a significant amount of time, thereby rendering reconfiguration impractical for implementing typical circuits.
Yet other approaches to increase the complexity and size of logic circuits have been to time multiplex the FPGA using additional configuration memory cells. Specifically, one configuration memory cell typically controls each programming point on an FPGA. FIG. 1 illustrates an exemplary configuration memory cell 100, which includes a conventional latch 101 operatively coupled to a select transistor 102. Configuration memory cell 100 can be loaded with configuration data 105 via select transistor 102, which is controlled by a configuration select signal 104. Once loaded into latch 101, configuration data 105 can be provided to CLB and interconnect logic 103.
In one exemplary time multiplexing approach described in U.S. Pat. No. 5,426,378, at least first and second arrays of configuration memory cells can be provided. For example, FIG. 2 illustrates a switching device (e.g. a multiplexer) 206 receiving inputs from a first configuration array 201 and a second configuration array 202. In one embodiment, a user's clock 204 can be divided into two phases. During a first phase, the configuration data in first configuration array 201 can be used, thereby configuring a CLB and interconnect matrix 205 in a first configuration. During a second phase, the configuration data in second configuration array 202 can be used, thereby configuring CLB and interconnect matrix 205 in a second configuration. In this embodiment, a third configuration array 203 can be provided, wherein the configuration data stored in this array does not change during reconfiguration. In this manner, where each CLB could previously implement one logic function during a cycle of the user's clock, each CLB can now implement two logic functions during the same cycle.
In another exemplary time multiplexing approach described in U.S. Pat. No. 5,583,450, each memory cell can be replaced with a random access memory (RAM) bit set. For example, FIG. 3 illustrates a bit set 300 that includes eight memory cells MC1–MC8. Each memory cell MC has a latch 301 and an associated select transistor 302. Memory cells MC1–MC8 are coupled to receive configuration data 303 and provide signals to a clocked latch 304.
In one embodiment, the configuration bits at the same memory cell location in each bit set on the FPGA are read out simultaneously to update the configuration of the CLBS and interconnect, thereby causing the CLBS to perform different logical functions and the interconnect to make different connections. In other words, by providing a bit set with eight memory cells for each FPGA programming point, an FPGA can effectively provide eight configurations. By reconfiguring the CLBS, the number of function generators in the CLB, typically conventional look up tables (“real LUTs”), needed to implement a given number of LUTs in a user circuit (“virtual LUTS”) are reduced by a factor of the number of configurations.
In either time multiplexing approach, the additional configuration memory cells increase logic density by dynamic re-use of the FPGA circuitry. Specifically, CLBs and interconnect are configured to perform some defined task at one instant and are reconfigured to perform another task at another instant. However, these additional configuration memory cells can cause significant complexity in their programming as well as in their operation. Moreover, these additional configuration memory cells can also undesirably take up significant silicon area. For example, a typical CLB could include between 360 and 564 programming points, wherein each programming point would be implemented by a bit set (e.g. bit set 300). Thus, instead of being configured by 360 to 564 memory cells in a non-time multiplexed FPGA, each CLB could be configured by as many as 4512 memory cells. (Note that this count can include many memory cells that are actually located in the interconnect, but are associated with a CLB.) Therefore, although offering significant advantages in logic density, a time multiplexed FPGA can have an unacceptable cost in silicon area.
Therefore, a need arises for a system and method of increasing functionality of an FPGA while minimizing silicon resources.